Circuit configuration for a capacitive sensor

ABSTRACT

The circuit configuration includes a measuring capacitor (K M1 ) having a variable capacitance, which is set by means of a physical measured quantity (p) to be detected, a reference capacitor (K Ref1 ) and a buffer amplifier (OV 1 ). An input of the buffer amplifier (OV 1 ) is at least temporarily coupled to the measuring capacitor (K M1 ) such that an output of the buffer amplifier (OV 1 ) supplies a signal voltage essentially proportional to a measurement voltage occurring on the measuring capacitor (K M1 ). At the beginning of each measuring cycle, the measuring capacitor (K M1 ) is discharged to a predetermined residual charge, whereas the reference capacitor (K Ref1 ) is charged to a predetermined reference charge. Afterwards, the reference charge is transferred as completely as possible from the reference capacitor (K Ref1 ) to the measuring capacitor (K M1 ). To this end, the input and output of the buffer amplifier (OV 1 ) are temporarily coupled to one another via the first reference capacitor (K Ref1 ) during operation. The circuit configuration thus supplies a signal voltage dependent on a reciprocal of the capacitance of the measuring capacitor and, in addition, has a current consumption that is practically independent of the instantaneous capacitance of the measuring capacitor (K M1 ).

The invention relates to a circuit arrangement for a capacitive sensor, as well as to a method for setting a signal voltage instantaneously representing a variable, physical, measured quantity, especially a static pressure of a fluid.

In EP-A 922 962, a circuit configuration for a capacitive sensor is disclosed, which includes:

-   -   a measuring capacitor having a variable capacitance, which is         set by means of a physical, measured quantity to be detected,         which measuring capacitor carries a charge proportional to the         instantaneously set capacitance,     -   a discharging reference capacitor and     -   an inverting amplifier     -   of which an input and an output are connected together via the         reference capacitor,     -   wherein the input of the amplifier is temporarily coupled with         the measuring capacitor such     -   that the charge of the measuring capacitor is transferred as         completely as possible onto the reference capacitor and     -   that the output of the amplifier supplies a signal voltage which         is essentially proportional to the capacitance of the measuring         capacitor.

It has been found to be disadvantageous with such a circuit configuration, among other things, that the charge applied to the measuring capacitor is dependent on its instantaneous capacitance and, consequently, current consumption of the circuit configuration can fluctuate in use over a wide range. The current consumption can reach undesirably high values therein, especially also for the not inconceivable case of a short circuit within the measuring capacitor.

An additional disadvantage of the mentioned circuit configuration arises in its application in a capacitive pressure sensor where the yielded signal voltage is proportional to the capacitance and, consequently, not proportional to the measured quantity being detected.

An object of the invention is, consequently, to provide a circuit configuration which is especially suited for a capacitive sensor, exhibits a current consumption with is practically independent of the instantaneous capacitance of the measuring capacitor, and produces a signal voltage dependent on the reciprocal of the capacitance of the measuring capacitor.

For solving the object, the invention provides, for a capacitive sensor, a circuit configuration, which includes:

-   -   a first measuring capacitor discharged to a predeterminable         residual charge and having a variable capacitance set by means         of a physical, measured quantity to be detected,     -   a first reference capacitor carrying a reference charge, and     -   a first buffer amplifier     -   of which an input is coupled at least temporarily with the first         measuring capacitor such that     -   an output of the first buffer amplifier delivers a first signal         voltage, which is essentially proportional to a measured voltage         occurring on the first measuring capacitor,     -   wherein input and output of the first buffer amplifier are         coupled during operation temporarily together via the first         reference capacitor such that the reference charge of the first         reference capacitor is transferred as completely as possible         onto the first measuring capacitor.

The invention additionally resides in a method for setting a signal voltage, which instantaneously represents a variable, physical, measured quantity, especially a static pressure of a fluid, which method includes the following steps:

-   -   causing a change in the capacity of an adjustable measuring         capacitor, such change corresponding with a change in the         measured quantity;     -   discharging the measuring capacitor to a predetermined residual         charge,     -   producing a reference charge on a reference capacitor,     -   transferring the reference charge from the reference capacitor         onto the measuring capacitor for producing a measurement voltage         instantaneously representing its capacity, and     -   amplifying the measurement voltage with an amplification of         about one for producing the signal voltage.

According to a first preferred development of the invention, the circuit configuration includes, for discharging the first measuring capacitor, a first switch, which places a first electrode of the first measuring capacitor temporarily at a first reference potential.

According to a second preferred development of the invention, a second electrode of the first measuring capacitor is at a fixed, second reference potential.

According to a third preferred development of the invention, the two reference potentials are equal for the first measuring capacitor, so that its residual charge is essentially equal to zero.

According to a fourth preferred development of the invention, the first reference capacitor is coupled with a first electrode to the output of the first buffer amplifier and, for charging of the first reference capacitor with the reference charge, a second switch is provided, which couples the first reference capacitor via a second electrode temporarily to an output of a supply electronics supplying the charging voltage.

According to a fifth preferred development of the invention, the circuit configuration includes for transferring the reference charge onto the first measuring capacitor a third switch temporarily coupling the second electrode of the first reference capacitor to the input of the first buffer amplifier.

According to a sixth preferred development of the invention, the circuit configuration includes a sample-hold circuit for sampling and holding the signal voltage.

According to a seventh preferred development of the invention, the circuit configuration additionally contains a second measuring capacitor and the input of the first buffer amplifier is temporarily coupled with the second measuring capacitor such that the output of the buffer amplifier delivers a signal voltage, which is essentially proportional to a measurement voltage occurring on the second measuring capacitor.

According to an eighth preferred development of the invention, the circuit configuration further includes:

-   -   a second reference capacitor carrying a reference charge and     -   a second buffer amplifier     -   of which an input is coupled at least temporarily with the first         measuring capacitor such that     -   an output of the second buffer amplifier delivers a second         signal voltage, which is essentially proportional to the         measurement voltage occurring on the first measuring capacitor,     -   wherein input and output of the second buffer amplifier are         temporarily coupled together in operation via the second         reference capacitor such that the reference charge is         transferred as completely as possible from the second reference         capacitor onto the first measuring capacitor.

According to a ninth preferred development of the invention, the circuit configuration further includes a reactive stage having a capacitance, which is as close as possible to a parasitic capacitance that partially appropriates the reference charge delivered from the first reference capacitor.

According to a tenth preferred development of the invention, the circuit configuration includes a conductor connecting the first measuring capacitor with the input of the first buffer amplifier, wherein the conductor has an actively protecting shield.

According to a first preferred development of the method of the invention, the signal voltage is sampled and temporarily held for producing a measurement signal reacting to the change in the measured quantity.

According to a second preferred development of the method of the invention, a charging voltage is applied to the reference capacitor for producing the reference charge, the application being for a sufficiently long time to cause a predetermined reference voltage drop across the reference capacitor.

According to a third preferred development of the method of the invention, the residual charge, to which the measuring capacitor is discharged, is about equal to zero.

The invention and advantages are explained below in more detail on the basis of examples of embodiments presented in the figures of the drawing; equal parts are provided in the figures with equal reference characters. In cases where it serves for clarity, repetition of already presented reference characters is avoided in subsequent figures.

FIG. 1 shows schematically a circuit configuration for a capacitive sensor,

FIG. 2 shows schematically signals versus time for the circuit configuration of FIG. 1,

FIG. 3 shows schematically a further development of the circuit configuration of FIG. 1 and

FIG. 4 shows schematically another further development of the circuit configuration of FIG. 1.

FIG. 1 shows schematically a circuit configuration for a capacitive sensor, particularly an absolute pressure sensor, a relative pressure sensor or a differential pressure sensor. The circuit configuration serves for delivering at an output of a first buffer amplifier OV₁ a clocked and cyclically updated signal voltage ΔU_(S1), which represents a capacitance CM, of an adjustable and/or a self-adjusting first measuring capacitor K_(M1) The buffer amplifier OV₁ can e.g. be an impedance converter.

The signal voltage ΔU_(S1) produced by the circuit configuration is preferably changed into a corresponding, especially digital, measurement signal x_(p) by means of an evaluation electronics AE of the sensor having the circuit configuration. Signal x_(p) can be forwarded e.g. via a data bus to an upstream measurements station. If required, the measurement signal x_(p) can also be an analog signal, e.g. a loop current in the range of 4 mA to 20 mA. The evaluation of such signal voltage outputs from amplifier circuits is basically known to those skilled in the art and, consequently, requires no further explanation. Corresponding embodiments for a circuit suitable as evaluation electronics AE are e.g. also available in the above-mentioned EP-A 922 962.

In the operation of the circuit configuration, the capacitance of the measuring capacitor K_(M1) is set by means of a variable, physical, measured quantity p, especially a static pressure, acting on the sensor, i.e. a change in the measured quantity p effects a corresponding change in the instantaneous capacitance of the measuring capacitor K_(M1).

For the already indicated case, that the physical, measured quantity p to be detected by means of the sensor is a static pressure, the measuring capacitor K_(M1) can e.g. be a capacitive pressure measuring cell with an elastically deformable membrane, which carries one of at least two capacitor plates and which, reacting to a change of the measured quantity with a change in flexure, adjusts a relative separation between the first and second capacitor plates. Structure and use of such pressure sensitive measuring capacitors are known per se to those skilled in the art, so that it is not necessary to consider such in more detail here. For examples of embodiments of such measuring capacitors, reference is made to U.S. Pat. No. 5,001,595, U.S. Pat. No. 5,005,421, U.S. Pat. No. 5,050,034, U.S. Pat. No. 5,079,953, U.S. Pat. No. 5,194,697, U.S. Pat. No. 5,400,489, U.S. Pat. No. 5,539,611. Of course, measuring capacitor K_(M1) can, if required, also be one that reacts with a measurable change of its capacitance to changes of other physical, measured quantities, such as e.g. a temperature and/or a dielectric constant.

As shown in FIG. 1, the measuring capacitor has a first electrode at an, especially fixed, first reference potential U_(M11), e.g. ground. Additionally, a second electrode of the measuring capacitor K_(M1) is coupled to an input of the buffer amplifier OV₁. In this way, a measurement voltage ΔU_(M1), as influenced by an instantaneous charge and the instantaneous capacitance C_(M1) of the measuring capacitor K_(M1), is sampled practically directly by means of the buffer amplifier OV₁ at its input side.

According to the invention, the measuring capacitor K_(M1) is discharged at the beginning of a measuring cycle to a defined residual charge Q_(Res1). For this purpose, a second reference potential U_(M12) is temporarily placed on the second electrode of the measuring capacitor K_(M1) during operation of the circuit configuration. A corresponding residual voltage, ΔU_(M1),0, of the measuring capacitor K_(M1) is thus given by: $\begin{matrix} {{\Delta\quad U_{{M1},0}} = {\frac{Q_{Res1}}{C_{M1}}.}} & (1) \end{matrix}$

Preferably for discharging the measuring capacitor K_(M1), the circuit configuration is provided, in parallel with capacitor K_(M1), with a first switch S₁₁, which, under control by a first, binary clock signal clk₁, serves for repeatedly, temporarily, and in predetermined manner, placing the second electrode of the measuring capacitor K_(M1) at the second reference potential U_(M12).

The reference potential U_(M12) is preferably identical to the reference potential U_(M11), so that the measuring capacitor K_(M1) in this case is, in effect, short-circuited during discharging. In this way, it can be assured in simple manner that the measuring capacitor K_(M1) is down to the predetermined residual charge Q_(Res1), here practically equal to zero, even already after a very short discharge time. In case required, the two reference potentials can, however, be selected to be different from one another.

Besides the measuring capacitor K_(M1), the circuit configuration includes additionally at least one first reference capacitor K_(Ref1) of predetermined, especially discretely adjustable, capacitance C_(Ref1), of which a first electrode is held at an instantaneously definite potential by the signal voltage ΔU_(S1). For this purpose, the reference capacitor K_(Ref1) is connected, especially fixedly, via its first electrode, as shown in FIG. 1, with the output of the buffer amplifier OV₁. It is noted here, additionally, that also the signal voltage ΔU_(S1) is preferably to be referenced to the second reference potential U_(M12) serving practically as the circuit null point.

In operation, the second electrode of the reference capacitor K_(Ref1) is connected at times with a charging voltage ΔU_(L) of a supply electronics VE such that a reference voltage ΔU_(Ref1) is set on the reference capacitor K_(Ref1). This reference voltage is essentially equal to an instantaneous difference, ΔU_(L)−ΔU_(S1), between the charging voltage and the signal voltage. Accordingly, the reference capacitor K_(Ref1) has a corresponding reference charge Q_(Ref1), whose level is given essentially by the product C_(Ref1)×ΔU_(Ref1). The charging voltage ΔU_(L) is here preferably referenced to the second reference potential U_(M12), like the residual voltage of the measuring capacitor K_(M1).

For the temporary application of the charging voltage ΔU_(L) on the reference capacitor K_(Ref1), the circuit configuration includes preferably a second switch S₁₂ coupling the reference capacitor and the supply electronics VE together. Switch S₁₂ is controlled by a second binary clock signal clk2, especially one in phase with the clock signal clk₁. Clock signals clk₁, clk₂ are here so formed, that, in operation of the circuit configuration, the two switches S₁₁, S₁₂ are opened before the beginning t₁ of a first phase t₁-t₂.

For determining the capacity C_(M1) according to the method of the invention, the measuring capacitor K_(M1) is discharged as completely as possible during the phase t₁-t₂ via the switch S₁₁, which is closed then at least for a time, down to the predetermined residual voltage ΔU_(M1),0. Practically simultaneously with the discharging of the measuring capacitor K_(M1), the reference capacitor K_(Ref1) is charged by means of the charging voltage ΔU_(L), which is supplied then via the closed switch S₁₂. In case required, the discharge of the measuring capacitor K_(M1) and the charging of the reference capacitor K_(Ref1) can, however, also be displaced in time in the phase t₁-t₂. At the phase end t₂ of the phase t₁-t₂, then both the switch S₁₁ and the switch S₁₂ are again opened.

The length of the phase t₁-t₂ is selected here such that at the latest at the phase end t₂ the measuring capacitor is discharged to the defined residual charge, e.g. Q_(Res1)=0. Additionally, also at the latest at the phase end t₂, the reference capacitor K_(Ref1) is to carry, as already mentioned, the reference charge, Q _(Ref1) =C _(Ref1)(ΔU _(L) −ΔU _(S1))  (2)

After the expiration of the phase t₁-t₂, the reference charge Q_(Ref1) is, during a second phase t₃-t₄ of the method of the invention, removed as much as possible from the reference capacitor K_(Ref1) and transferred as much as possible onto the measuring capacitor K_(M1), such that, at a phase end t₄ of the phase t₃-t₄, the following relationship holds for practical purposes: C _(M1)(ΔU _(M1) +ΔU _(M1,0))=Q _(Ref1) +Q _(Res1)  (3).

On the basis of Equations (1) and (2), Equation (3) now leads to the following expression for the measurement voltage ΔU_(M1): $\begin{matrix} {{\Delta\quad U_{M1}} = {\frac{C_{Res1}}{C_{M1}}\Delta\quad{U_{Refl}.}}} & (4) \end{matrix}$

As can be seen from Equation (4), the measurement voltage ΔU_(M1) in the circuit configuration of the invention is practically proportional to the reciprocal of the capacitance C_(M1) of the measuring capacitor K_(M1) This, in turn, has the advantage, that use of the circuit configuration of the invention in a capacitive pressure sensor, in which the capacitance C_(M1) is known to depend on a reciprocal of the pressure to be measured, means that a pressure increase causes, apart from relevant amplification factors, proportionately also an increase of the measurement voltage ΔU_(M1).

For transferring the reference charge QRef1 onto the measuring capacitor K_(M1), the circuit configuration of FIG. 1 includes, preferably, a third switch S₁₃, which, turned on by a third clock signal clk₃ shifted in phase from the clock signals clk₁, clk₂, connects the second electrode of the reference capacitor K_(Ref1) with the input of the buffer amplifier OV₁.

According to FIG. 2, the switch S₁₃, previously open, especially during the phase t₁-t₂, is closed during the course of phase t₃-t₄. An instantaneous signal level difference arising directly after the closing of the switch S₁₃ between the input and the output of the buffer amplifier OV₁ is practically immediately equalized thereby. Expressed in other terms, the reference voltage ΔU_(Ref1) lying across the reference capacitor K_(Ref1) is set to null following the closing of switch S₁₃, whereby inevitably the reference capacitor K_(Ref1) is also discharged. A discharge current flowing in this regard transports the reference charge previously carried by the reference capacitor K_(Ref1) practically completely to the measuring capacitor K_(M1).

Both the mentioned switch S₁₃ and also the switches S₁₁, S₁₂ can, in manner known to those skilled in the art, be realized by means of transistors, especially field-effect transistors. It should be noted at this point additionally that the switches S₁₁, S₁₂, S₁₃ are drawn as normally open, thus as switches that close when the associated clock signal clk₁, clk₂, clk₃, respectively, turns high. Should it be required, however, the switches S₁₁, S₁₂, S₁₃ can also be embodied as normally closed, which are each then closed, when the associated clock signal is low. Naturally, the clock signals are to be inverted in appropriate manner for this case.

As can be seen from FIG. 2, the clock signals clk₁, clk₂, clk₃ are, in any case, to be formed such that the switch S₁₃ is, at most, always only closed when the two switches S₁₁, S₁₂ are open. In case required, the clock signals have for this, as, in fact, shown in FIG. 2, different pulse-to-pause relationships from one another. For suppressing interference couplings onto the signal voltage, the clock signals can, as e.g. also described in EP-A 922 962, additionally be varied in operation with respect to their clock frequency or their phase position, while maintaining the above-described boundary conditions.

The clock signals clk₁, clk₂, clk₃ can e.g. be produced by an appropriate control electronics SE of the sensors having the circuit configuration.

According to a preferred further development of the method of the invention, for producing the measurement signal x_(p), the signal voltage ΔU_(S1) is sampled and held during a third phase t₄-t₅ following the phase t₃-t₄ by a sample-hold circuit SH₁ controlled by a sample clock signal clk_(SH1). The sample clock signal clk_(SH1) is, as also shown schematically in FIG. 2, so formed that the sample-hold circuit SH₁ is activated only after the closing of the switch S₁₃ and after the updating of the signal voltage ΔU_(S1), when it is then coupled to the output of the buffer amplifier OV₁ carrying this. Additionally, a pulse width of the sample clock signal clk_(SH1) is to be dimensioned such that the sample-hold circuit SH₁ is separated again from the buffer amplifier OV₁ at the latest at the end t₅ of the phase t₄-t₅.

The sample-hold circuit SH₁ can be followed, in manner known to those skilled in the art, with an analog-to-digital converter serving for producing a digital signal representing the signal voltage ΔU_(S1). For correcting any possible drift of the charging voltage ΔU_(L), the analog-to-digital converter (not shown here) is advantageously coupled with a reference input, e.g. to a reference voltage directly proportional to the charging voltage ΔU_(L).

Investigations have additionally shown that, in concrete realizations of the circuit configuration of the invention, the case can arise that, for practical cases, unavoidable, parasitic capacitances of the circuit configuration can be so formed and so connected that a significant fraction of the reference charge Q_(Ref1), from about 1% to 10%, is not transferred onto the measuring capacitor K_(M1). This, in turn, would cause a significant error in the signal voltage ΔU_(S1). Additionally, such parasitic capacitances, which e.g. can be formed by usually applied overvoltage protection circuits, by conductor capacitances or by input capacitances of the buffer amplifier OV₁, are most often variable, so that their influence on the signal voltage ΔU_(S1) cannot practically be predicted with accuracy ahead of time.

Therefore, for improving the accuracy of the signal voltage ΔU_(S1) according to a preferred, further development of the invention, a reactive stage BS₁ is provided, having a capacitance C_(BS1), which, on the one hand, is as equal as possible to a parasitic capacitance C_(PS1) partially appropriating the reference charge Q_(Ref1), and which, on the other hand, also changes in operation in an at least similar manner. In order to achieve as accurate a mimicking of this parasitic capacitance C_(PS1) as possible, the reactive stage BS₁ is designed essentially identically to the circuit structure PS1 forming the parasitic capacitance C_(PS1).

For compensating the fraction of the reference charge Q_(Ref1) transferred onto the circuit structures PS1, the capacitance C_(BS1) of the reactive stage BS, is charged, according to a preferred, further development of the method of the invention, in a fourth phase t₅-t₆ by means of the signal voltage ΔU_(S1). For this purpose, a fourth switch S₁₄ is provided in the circuit configuration in the case of this further development of the invention. Switch S₁₄ is controlled, as shown in FIG. 3, by a fourth clock signal clk₄ and connects a first electrode of the reactive stage BS₁ with the output of the buffer amplifier OV₁ carrying the signal voltage ΔU_(S1).

A charge produced in this way in the reactive stage BS₁ is distributed by means of a fifth switch S₁₅ controlled by a fifth clock signal clk₅ finally during a fifth phase t₇-t₈ at least partially onto the measuring capacitor K_(M1) discharged as described above and onto the circuit structures PS1 discharged in the same way. The phase t₇-t₈ happens, as can be seen clearly from FIG. 2, practically between the two phases t₁-t₂, t₃-t₄ of a measuring cycle following on the charging of the reactive stage BS, in phase t₇-t₈.

In this further development of the method of the invention, the following approximation can hold for the measurement voltage ΔU_(M1), provided that, as above, the parasitic capacitance C_(PS1) lies in the range from about 1% to 10% of the measurement capacitance C_(M1) and assuming that both the parasitic capacitance C_(PS1) and the measurement capacitance C_(M1) approximately do not change over a time period large in comparison to the period of a measuring cycle: $\begin{matrix} {{\Delta\quad U_{M1}} = {\frac{C_{Res1}}{C_{M1} + C_{PS1} - C_{BS1}}\Delta\quad{U_{Refl}.}}} & (5) \end{matrix}$

As easily understandable on the basis of Equation 5, this approximation corresponds to the case where C_(PS1) is equal to C_(BS1), Equation 4. The assumption made in this, that the capacitances C_(PS1), C_(M1), change relatively slowly during two adjoining measuring cycles, can be easily fulfilled by a correspondingly high repetition rate of the measuring cycles, thus by choosing an appropriately high frequency for the clock signals. It should also be noted at this point that this approximation is ever so more accurate, the smaller the parasitic capacitance C_(PS1) is in comparison to the measurement capacitance.

It has also been found that, besides the mentioned parasitic capacitances, also interference voltages, which occur along the signal transfer path extending between the measuring capacitor K_(M1) and the buffer amplifier OV₁, can be a further cause for possible disturbing of the signal voltage ΔU_(S1).

For the suppression of such disturbances on the signal voltage ΔU_(S1), a preferred further development of the invention provides between the first electrode of the measuring capacitor K_(M1) and the input of the buffer amplifier OV₁ a conductor VL, which is at least sectionally shielded. In order to prevent a distortion of the signal voltage ΔU_(S1) because of usually not constant, conductor capacitances additionally introduced into the signal transmission path by this conductor VL, this further development additionally includes a galvanic connection between a shield GD, especially a coaxial shield, of the conductor VL and the output of the buffer amplifier OV₁. This known measure, also known as active guarding or “accompanying shield”, serves for discharging as much as possible a conductor capacitance formed between the first electrode of the measuring capacitor K_(M1) and the shield GD, or at least to maintain a constant charge therein, to the extent possible.

For the case where, as is usual e.g. in the measurement of pressure differences, a capacitance CM2 of a second measuring capacitor K_(M2) is to be registered in parallel with the measurement of the capacitance C_(M1) of the measuring capacitor K_(M1), at least a second measured value acquisition stage practically identical to the above-described first measured value acquisition stage can be used. Thus, whereas the first stage contains at least the measuring capacitor K_(M1), the reference capacitor K_(Ref1), the buffer amplifier OV₁ and the switches S₁₁, S₁₂, S₁₃, the second stage contains at least a second measuring capacitor K_(M2), a second reference capacitor K_(Ref2), a second buffer amplifier OV₂ and a sixth, seventh and eighth switch S₂₁, S₂₂, S₂₃. At the output of the buffer amplifier OV₂, a second signal voltage ΔU_(S2) can be sampled, which represents a measurement voltage drop ΔU_(M2) across the measuring capacitor K_(M2). The corresponding clock signals clk₁, clk₂, clk₃ can serve e.g. for controlling the switches S₂₁, S₂₂, S₂₃. See FIG. 4.

Preferably, the evaluation electronics AE in this further development of the invention includes also a second sample-hold circuit SH₂ for the signal voltage ΔU_(S2) delivered from the second measured value acquisition stage.

It has additionally been found with this further development of the invention that, especially for the case where the two measured value acquisition stages have different transfer behaviors from one another, caused e.g. by small tolerance variations in the individual components, a cyclic exchanging of the individual, identically acting components of the measured value acquisition stages, thus e.g. of both buffer amplifiers OV₁, OV₂ and/or both reference capacitors K_(Ref1), K_(Ref2) and/or, in some cases, both sample-hold circuits SH₁, SH₂ delivers, on average, the most accurate measurement results. The exchanging of individual components can e.g. occur by means of a simple switching mechanism composed of a first, second, third and fourth change-over switch W₁₁, W₁₂, W₂₁ and W₂₂, which switches (after some, e.g. about 10 to 100, repetitions of the above-described measuring cycles encompassing at least the phases t₁-t₂, t₃-t₄) are moved as synchronously as possible out of the shown switch positions into the respective alternate positions, and vice versa.

The first measured value acquisition stage of the proposed circuit configuration and, if present, also the second measured value acquisition stage and/or the reactive stage BS₁ are preferably realized in a monolithic structural form, e.g. integrated into a single ASIC component. This has, besides a very small space requirement for the circuit configuration, e.g. also the advantage that also the second measured value acquisition stage can be manufactured very simple as an identical duplicate of the first measured value acquisition stage. Likewise, also the reactive stage BS₁ can, in this way, be matched very easily to the switching structures PS1 forming the parasitic capacitance. 

1. A circuit configuration for a capacitive sensor, which configuration comprises: a first measuring capacitor (K_(M1)) of variable capacitance discharged to a predeterminable residual charge and having a variable capacitance, which is set by means of a physical, measured quantity (p) to be detected, a first reference capacitor (K_(Ref1)) carrying a reference charge, and a first buffer amplifier (OV₁), of which an input is coupled at least temporarily with the first measuring capacitor (K_(M1)) such that an output of the first buffer amplifier (OV₁) delivers a first signal voltage, which is essentially proportional to a measured voltage occurring on the first measuring capacitor (K_(M1)), wherein input and output of the first buffer amplifier (OV₁) are coupled during operation temporarily together via the first reference capacitor (K_(Ref1)) such that the reference charge of the first reference capacitor (K_(Ref1)) is transferred as completely as possible onto the first measuring capacitor (K_(M1)).
 2. Circuit configuration as claimed in claim 1, further comprising, for discharging the first measuring capacitor (K_(M1)), a first switch (S₁₁), which places a first electrode of the first measuring capacitor (K_(M1)) temporarily at a first reference potential.
 3. Circuit configuration as claimed in claim 2, wherein a second electrode of the first measuring capacitor (K_(M1)) is at a fixed, second reference potential.
 4. Circuit configuration as claimed in claim 3, wherein the two reference potentials are equal for the first meeting capacitor (K_(M1)), so that its residual charge is essentially equal to zero.
 5. Circuit configuration as claimed in claim 1, wherein the first reference capacitor (K_(Ref1)) is coupled with a first electrode to the output of the first buffer amplifier (OV₁) and wherein, for charging the first reference capacitor (K_(Ref1)) with the reference charge, a second switch (S₁₂) is provided, which couples the first reference capacitor (K_(Ref1)) via a second electrode temporarily to an output of a supply electronics (VE) supplying the charging voltage.
 6. Circuit configuration as claimed in claim 1, further comprising, for transferring the reference charge onto the first measuring capacitor (K_(M1)), a third switch (S₁₃) temporarily coupling the second electrode of the first reference capacitor (K_(Ref1)) to the input of the first buffer amplifier (OV₁).
 7. Circuit configuration as claimed in claim 1, further comprising a sample-hold circuit (SH₁) for sampling and holding the signal voltage.
 8. Circuit configuration as claimed in claim 1, wherein a second measuring capacitor (K_(M2)) is provided and wherein the input of the first buffer amplifier (OV₁) is temporarily coupled with the second measuring capacitor (K_(M1)) such that the output of the buffer amplifier (OV₁) delivers a signal voltage, which is essentially proportional to a measurement voltage occurring on the second measuring capacitor (K_(M1)).
 9. Circuit configuration as claimed in claim 8, further comprising: a second reference capacitor (K_(Ref2)) carrying a reference charge and a second buffer amplifier (OV₂) of which an input is coupled at least temporarily with the first measuring capacitor (K_(M1)) such that an output of the second buffer amplifier (OV₂) delivers a second signal voltage, which is essentially proportional to the measurement voltage occurring on the first measuring capacitor (K_(M1)), wherein input and output of the second buffer amplifier (OV2) are temporarily coupled together in operation via the second reference capacitor (K_(Ref2)) such that the reference charge is transferred as completely as possible from the second reference capacitor (K_(Ref2)) onto the first measuring capacitor (K_(M1)).
 10. Circuit configuration as claimed in claim 1, further comprising a reactive stage (BS₁) having a capacitance, which is as close as possible to a parasitic capacitance that partially appropriates the reference charge delivered from the first reference capacitor (K_(Ref1)).
 11. Circuit configuration as claimed in claim 1, wherein a conductor (VL) connecting the first measuring capacitor (K_(M1)) with the input of the first buffer amplifier (OV₁) has an actively protecting shield (GD).
 12. Sensor with a circuit configuration as claimed in claim
 1. 13. Method for setting a signal voltage, which represents instantaneously a variable, physical, measured quantity (p), especially a static pressure of a fluid, which method comprises the following steps: causing a change in the capacitance of an adjustable measuring capacitor (K_(M1)), such change corresponding with a change in the measured quantity (p); discharging the measuring capacitor (K_(M1)) to a predetermined residual charge, producing a reference charge on a reference capacitor (K_(Ref1)), transferring the reference charge from the reference capacitor (K_(Ref1)) onto the measuring capacitor (K_(M1)) for producing a measurement voltage instantaneously representing its capacity, and amplifying the measurement voltage with an amplification of about one for producing the signal voltage.
 14. Method as claimed in claim 13, wherein the signal voltage is sampled and temporarily held for producing a measurement signal (x_(p)) reacting to the change in the measured quantity (p).
 15. Method as claimed in claim 13, wherein a charging voltage is applied to the reference capacitor (K_(Ref1)) for producing the reference charge, the application being for a sufficiently long period of time to cause a predetermined reference voltage drop across the reference capacitor.
 16. Method as claimed in claim 13, wherein the residual charge, to which the measuring capacitor (K_(Ref1)) is discharged, is about equal to zero. 